The present invention relates to a nonvolatile semiconductor memory and, more particularly, to an improvement in an ultraviolet ray erasable and programmable read-only memory (to be referred to as an EPROM hereinafter).
FIG. 1 shows a sectional structure of a memory cell transistor constituting an EPROM cell. In FIG. 1, reference numeral 41 denotes a semiconductor substrate (e.g., a p.sup.- -type silicon substrate); 42, an n.sup.+ -type source region; 43, an n.sup.+ -type drain region; 44, a first gate insulating film; 45, a floating gate; 46, a control gate; and 47, a second gate insulating film. In this cell, when a high voltage is applied between regions 43 and 42 and between substrate 41 and gate 46, electrons e.sup.- of high energy accelerated by a high electric field between the drain and the source are attracted by gate 45 of a positive potential and injected therein, thereby writing data. Note that when no high voltage is applied to region 43 or 46, injection of electrons does not occur. The number of injected electrons (write amount) is linearly increased due to an increase in electric field in a channel direction when an effective channel length of the memory cell transistor is shortened.
FIG. 2 shows an equivalent circuit in which an EPROM cell transistor having the arrangement shown in FIG. 1 is applied to a memory cell array arranged in a matrix of 1024 rows.times.1024 columns. One of cell transistors (MC1, MC2, . . . , MC1024) of one column of this array is selected to write data using a write control transistor (TP). That is, the respective drains of cell transistors MC1, MC2, . . . , are commonly connected to bit line BL, and line BL is connected to sense amplifier SA. MOS transistor TP (an equivalent resistor of which in an ON state is represented by Rp in FIG. 2), which is switched by read/write control signal R/W, is connected between line BL and node WN to which write voltage Vpp is applied. The respective sources of transistors MC1, MC2, . . . are commonly connected and then directly connected to ground node GN, and different selection signals SS1, SS2, . . . are supplied to the respective gates thereof.
The following discussion assumes that transistor MC1 is selected and other transistors MC2 to MC1024 are not selected. When an effective channel length of each cell transistor is shortened, the degree of capacitive coupling between region 43 and gate 45 is relatively increased, and a floating gate potential of each of non-selected transistors MC2 to MC1024 is increased. When this potential exceeds a gate threshold voltage of the cell transistor when viewed from the floating gate, a small cell current begins to flow between the drain and the source of the non-selected cell transistor, and a punch through state occurs due to the capacitive coupling. In this case, although the current flowing through one non-selected cell transistor is small, a total current of all the non-selected cell transistors is very large and cannot be neglected in a large-capacity EPROM. The resistance of resistor Rp in an ON state of transistor TP is about 1 k.OMEGA.. Therefore, assuming that the cell current of each non-selected cell transistor is 1 .mu.A, the total cell current of the 1023 non-selected cell transistors is about 1 mA, and when this current of 1 mA flows through resistor Rp, a drain voltage of transistor MC1 is less than voltage Vpp by about 1 V. As a result, a write speed is undesirably decreased.
As is apparent from the above description, a write speed of the cell transistor has an optimal value with respect to an effective channel length of the transistor.
This is represented by solid line L1 in FIG. 3 as a result of simulation performed for a typical cell structure. In order to obtain write time 100 .mu.s (10.sup.-4 sec) or less, a channel length has an allowance (allowable variation width) of .+-.0.2 .mu.m (a central value of which is about 1.07 .mu.m).
In order to increase the above channel length allowance, an ion implantation dose for controlling the gate threshold voltage of the cell transistor may be increased. Dotted line L2 of FIG. 3 represents a simulation result of a cell, an ion implantation dose of which is increased by, e.g., 25% more than the cell represented by line L1 in FIG. 3. In this cell, in order to obtain a write L. time of 100 .mu.s, the channel length has an allowance of .+-.0.24 .mu.m.
The increased allowance of the channel length of the cell transistor represented by line L2 results from improved electron injection efficiency when the channel length is larger than the central value (.about.1.07 .mu.m). A punch through withstand voltage is increased by an increase in a threshold voltage when the value of the channel length is smaller than the central value.
However, in order to adjust the ion implantation dose of the cell to increase the allowance of the channel length, ion implantation must be performed for the cell and an element of a cell peripheral circuit in different steps, so that an additional photoetching step is undesirably performed. In addition, adjustment of the ion implantation dose leads to a decrease in cell current and/or an increase in capacitance of the bit line, thereby increasing an access time of the memory cell.